The present invention relates, in general, to the field of integrated circuit double data rate (xe2x80x9cDDRxe2x80x9d) synchronous dynamic random access memory (xe2x80x9cSDRAMxe2x80x9d) devices. More particularly, the present invention relates to a system and method for supporting sequential burst counts in DDR SDRAM memory devices.
SDRAM memory devices function somewhat differently than conventional random access memory devices such as DRAM and take advantage of the fact that most computer system memory access are, in fact, sequential. Consequently, SDRAM devices are designed to fetch the initial and following bits in a burst as quickly as possible. An on-chip burst counter allows the column portion of the address to be incremented rapidly in order to significantly speed retrieval of information in sequential read operations. The associated memory controller furnishes the first column address location and size of the block of memory to be accessed and the SDRAM memory device itself provides the read out bits as fast as the central processing unit (xe2x80x9cCPUxe2x80x9d) can take them, utilizing a clock to synchronize the timing between the CPU and memory device.
Historically, in order to synchronize data transfers among system logic devices, data transfers to/from conventional DRAM devices would be initiated on either the rising (the transition from logic level xe2x80x9czeroxe2x80x9d to xe2x80x9conexe2x80x9d) or falling (the transition from logic level xe2x80x9conexe2x80x9d to xe2x80x9czeroxe2x80x9d) edge of a clock signal. DDR SDRAM memory devices differ from conventional SDRAM by enabling output operations to occur on both the rising and falling edges of the clock, thereby effectively doubling the device""s output frequency without increasing the actual clock frequency.
DDR SDRAM device functionality is specified by a Joint Electron Devices Engineering Counsel (xe2x80x9cJEDECxe2x80x9d) standard and such memories are able to achieve this effective doubling of the device""s bandwidth by reading of data on both the rising and falling edges of each clock cycle. In DDR SDRAM devices, the first column address of a burst is supplied on the rising edge of the clock. However, the address for the data to be output on the falling edge of the clock may be obtained at this point in time in high-speed devices in order to be able to meet the data frequency requirements. In this case, the least significant address bit (AO) does not go to the column decoder since two sequential bits are always accessed. Only higher order bits are used to select a column, however, the least significant bit does determine the next sequential state for the higher order bits in a sequential accessing mode. One or more of the higher order address bits will be different for the rising and falling edge data any time AO=1 for rising edge data giving rise to the need for efficiently generating the address for pre-fetching the falling edge data. For example, if the first address for a burst of eight bits of data (A2 A1 A0) is 000, the next sequential address required is 001 so the actual column address (A2 A1) is the same for rising and falling edge data. However, if the first address is 001, the next sequential address is 010 and the actual column address is different for the rising and falling edge data.
In order to support sequential burst counts in DDR SDRAM memory devices, all data to be potentially accessed, regardless of actual count sequence, could be pre-fetched. Thereafter, decisions may be made as to what addresses were actually read from, or written to, based on the count sequence, type and starting address. However, pre-fetching all potentially accessed data is not an efficient technique if the data will ultimately not be used, such as when a particular burst sequence is interrupted.
In the particular embodiment disclosed herein, each memory bank is divided into halves, corresponding to Even (A0c=0) and Odd (AOc=1). The Odd and even sections have separate buffers, counters and address busses for all column addresses associated with the maximum burst length ever required, for example, two bits if the maximum burst length is eight bits since AO is always 0 for the even section and 1 for the Odd section. All other column address bits are on a common bus shared by the Odd and even sections.
As the column addresses are loaded, the buffers associated with the Even bus check to determine if the pad address xe2x80x9cYxe2x80x9d or xe2x80x9cY+1xe2x80x9d should be loaded. Loading xe2x80x9cY+1xe2x80x9d is necessary to support sequential counting if the start address is Odd (AOc=1). xe2x80x9cYxe2x80x9d selects in the Odd and Even banks are then selected and incremented, concurrently. Nevertheless, the Even field is always xe2x80x9cY+1xe2x80x9d, that is, YEven=YOdd+1.
Stated another way, the system and method of the present invention advantageously loads the xe2x80x9cEvenxe2x80x9d section of the bank with xe2x80x9cY+1xe2x80x9d initially (if required), then the first access, and all subsequent ones, continue with no knowledge that the xe2x80x9cYxe2x80x9d address in the xe2x80x9cEvenxe2x80x9d field is different from that in the xe2x80x9cOddxe2x80x9d field. Odd and Even column paths are also, effectively electrically the same resulting in no appreciable difference in critical timing or substantial path layout differences.
Particularly disclosed herein is a memory device including a memory array comprising first and second portions thereof, the memory array being addressable by corresponding first and second column decoders. First, second and third buffers are coupled to first, second and third address output busses on which the column addresses may be placed for accessing data in first and second portions of the memory array. The first and second address output busses are respectively coupled to first and second column decoders with the third address output bus common to both the first and second memory portions. First and second load circuits are provided, each load circuit being interposed between the first and second buffer circuits respectively and a first portion of the address input bus, such portion being associated with the burst counter address bits and being common to both first and second load circuits. The second load circuit being selectively operative to add an integer amount to the first set of address bits for input to the second buffer. Third buffers are interposed between a second portion of the input address bus and the third column address output bus. First and second burst counters are provided, each counter is interposed between the output address bus and the first and second buffers respectively and each is operative to count from a starting address in sequential order coupling the sequential addresses to the input of the first and second buffers respectively.
Further disclosed herein is method for enabling sequential burst counts in a memory device comprising the steps of partitioning a memory array into first and second portions thereof; each of the first and second portions having an associated first and second column decoder respectively. First, second and third buffers are coupled to first, second and third address output busses on which the column addresses may be placed for accessing data in first and second portions of the memory array. The first and second address output busses are respectively coupled to first and second column decoders with the third address output bus common to both the first and second memory portions. First and second load circuits are provided, each load circuit being interposed between the first and second buffer circuits respectively and a first portion of the address input bus, such portion being associated with the burst counter address bits and being common to both first and second load circuits. The second load circuit being selectively operative to add an integer amount to the first set of address bits for input to the second buffer. Third buffers are interposed between a second portion of the input address bus and the third column address output bus. First and second burst counters are provided, each counter is interposed between the output address bus and the first and second buffers respectively and each is operative to count from a starting address in sequential order coupling the sequential addresses to the input of the first and second buffers respectively. A start address for a burst access to the memory array is determined and an integer amount is selectively added to an address directed to the second buffer if the start address is indicative of an address in the first portion of said memory array.